All the coursework has to be done in VHDL. Coursework handed in using another language will be marked as zero.

? Coursework must be typeset. ? Never use screenshots or photograph of code in your coursework. Typeset code within your

coursework report using a monospace font (e.g. courier new). ? Never use photographs of waveforms in your coursework. Use a proper screen capture tool to include

a high resolution screenshot in your coursework.

a) Consider the register bank of the educational processor (file cpuregbank.vhd of labcpu):

The objective is to create a testbench for this circuit, and simulate the a few operations including storing data in it as well as retrieving data from it.

In order to do this, use the file cpuregbank.vhd which is in labcpu zipfile. The file dffre.vhd is also required as it is used internally by the register bank.

H7068 DIGITAL SYSTEMS AND MICROPROCESSOR DESIGN: COURSEWORK 2019

The ports of cpuregbank are:

clk : in STD_LOGIC; — Clock rst : in STD_LOGIC; — Reset signal (active high) d : in STD_LOGIC_VECTOR(7 downto 0) — Data to write to a register

— (when rwren is enabled) rwren : in STD_LOGIC — Set to 1 to write d into register rwr rwr : in STD_LOGIC_VECTOR(1 downto 0) — Selects which register to write to. — The register encoding is identical — to that used in the assembler

— instruction encoding. rrd1 : out STD_LOGIC_VECTOR(1 downto 0) — Select which register is

— mapped to q1 rrd2 : out STD_LOGIC_VECTOR(1 downto 0) — Select which register is

— mapped to q2 q1 : out STD_LOGIC_VECTOR(7 downto 0) — Content of register selected by rrd1 q2 : out STD_LOGIC_VECTOR(7 downto 0) — Content of register selected by rrd2 dbg_qa : in STD_LOGIC_VECTOR(7 downto 0) — This is a debug signal which has

— the content of register RA. It is — used in the lab to display the — register content on the 7-segment — display. (A production processor — would not have this signal)